? semiconductor components industries, llc, 2010 january, 2010 ? rev. 2 1 publication order number: nb7v33m/d nb7v33m 1.8v / 2.5v, 10ghz 4 clock divider with cml outputs multi ? level inputs w/ internal termination description the nb7v33m is a differential 4 clock divider with asynchronous reset. the differential clock inputs incorporate internal 50 termination resistors and will accept lvpecl, cml and lvds logic levels. the nb7v33m produces a 4 output copy of an input clock operating up to 10 ghz with minimal jitter. the reset pin is asserted on the rising edge. upon powerup, the internal flip flops will attain a random state; the reset allows for the synchronization of multiple nb7v33m?s in a system. the 16 ma differential cml output provides matching internal 50 termination which guarantees 400 mv output swing when externally receiver terminated with 50 to v cc . the nb7v33m is the 4 version of the nb7v32m ( 2) and is offered in a low profile 3 mm x 3 mm 16 ? pin qfn package. the nb7v33m is a member of the gigacomm ? family of high performance clock products. application notes, models, and support documentation are available at www.onsemi.com. features ? maximum input clock frequency > 10 ghz, typical ? 260 ps typical propagation delay ? 35 ps typical rise and fall times ? differential cml outputs, 400 mv peak ? to ? peak, typical ? operating range: v cc = 1.71 v to 2.625 v with gnd = 0 v ? internal 50 input termination resistors ? random clock jitter < 0.8 ps rms ? qfn ? 16 package, 3 mm x 3 mm ? ? 40 o c to +85 c ambient operating temperature ? these are pb ? free devices a = assembly location l = wafer lot y = year w = work week = pb ? free package *for additional marking information, refer to application note and8002/d. marking diagram* qfn16 mn suffix case 485g http://onsemi.com see detailed ordering and shipping information in the package dimensions section on p age 9 of this data sheet. ordering information 16 nb7v 33m alyw 1 q0 q0 figure 1. simplified logic diagram vtclk clk clk 50 vtclk 50 (note: microdot may be in either location) 1 reset r 4 v refac v cc gnd
nb7v33m http://onsemi.com 2 figure 2. pin configuration (top view) vrefac gnd gnd gnd vcc r vcc vcc q q vcc vtclk clk clk vtclk 5678 16 15 14 13 12 11 10 9 1 2 3 4 nb7v33m exposed pad (ep) vcc table 1. truth table clk clk r q q x x h l h z w l clk 4 clk 4 z = low to high transition w = high to low transition x = don?t care table 2. pin description pin name i/o description 1 vtclk ? internal 50 termination pin for clk 2 clk lvpecl, cml, lvds input non ? inverted differential clk input. note 1. 3 clk lvpecl, cml, lvds input inverted differential clk input. note 1. 4 vtclk ? internal 50 termination pin for clk 5 vrefac ? internally generated output voltage reference for capacitor ? coupled inputs, only 6 gnd ? negative supply voltage 7 gnd ? negative supply voltage 8 gnd ? negative supply voltage 9 v cc ? positive supply voltage. note 2. 10 q cml output inverted differential output 11 q cml output non ? inverted differential output 12 v cc ? positive supply voltage. note 2. 13 v cc ? positive supply voltage. note 2. 14 v cc ? positive supply voltage. note 2. 15 r lvcmos input asynchronous reset input. internal 75 k pulldown to gnd. 16 v cc ? positive supply voltage. note 2. ? ep ? the exposed pad (ep) on the qfn ? 16 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is electrically connected to the die, and must be electrically and thermally con- nected to gnd on the pc board. 1. in the dif ferential configuration when the input termination pins (vtclk/vtclk ) are connected to a common termination voltage or left open, and if no signal is applied on clk/clk input, then the device will be susceptible to self ? oscillation. q/q outputs have internal 50 source termination resistors. 2. all v cc and gnd pins must be externally connected to a power supply for proper operation.
nb7v33m http://onsemi.com 3 table 3. attributes characteristics value esd protection human body model machine model > 4 kv > 200 v r pd ? reset input pulldown resistor 75 k moisture sensitivity (note 3) qfn16 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 190 meets or exceeds jedec spec eia/jesd78 ic latchup test 3. for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v 3.0 v v in positive input voltage gnd = 0 v ? 0.5 to v cc +0.5 v v inpp differential input voltage |d ? d | 1.89 v i in input current through r t (50 resistor) 40 ma i out output current through r t (50 resistor) 40 ma i vfrefac vrefac sink/source current 1.5 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 4) 0 lfpm 500 lfpm qfn ? 16 qfn ? 16 42 35 c/w jc thermal resistance (junction ? to ? case) (note 4) qfn ? 16 4 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
nb7v33m http://onsemi.com 4 table 5. dc characteristics positive cml output v cc = 1.71 v to 2.625 v; gnd = 0 v; t a = ? 40 c to 85 c (note 5) symbol characteristic min typ max unit power supply current i cc power supply current (inputs and outputs open) v cc = 2.5 v 5% v cc = 1.8 v 5% 95 85 115 100 ma cml outputs v oh output high voltage (note 6) v cc = 2.5 v v cc = 1.8 v v cc ? 30 2470 1770 v cc ? 10 2490 1790 v cc 2500 1800 mv v ol output low voltage (note 6) v cc = 2.5 v v cc = 1.8 v v cc ? 650 1850 v cc ? 600 1200 v cc ? 550 1950 v cc ? 500 1300 v cc ? 450 2050 v cc ? 400 1400 mv differential inputs driven single ? ended (note 7) (figures 5 & 6) v th input threshold reference voltage range (note 8) 1050 v cc ? 100 mv v ih single ? ended input high voltage v th + 100 v cc mv v il single ? ended input low voltage gnd v th ? 100 mv v ise single ? ended input voltage (v ih ? v il ) 200 1200 mv vrefac v refac output reference voltage @100 a for capacitor ? coupled inputs, only v cc = 2.5 v v cc = 1.8 v v cc ? 850 v cc ? 750 v cc ? 500 v cc ? 450 mv differential inputs driven differentially (figures 7 & 8) (note 9) v ihd differential input high voltage 1100 v cc mv v ild differential input low voltage gnd v cc ? 100 mv v id differential input voltage (v ihd ? v ild ) 100 1200 mv v cmr input common mode range (differential configuration, note 10) (fig- ure 9) 1050 v cc ? 50 mv i ih input high current (vtx/vtx open) ? 150 150 a i il input low current (vtx/vtx open) ? 150 150 a control input (reset pin) v ih input high voltage for control pin v cc ? 200 v cc mv v il input low voltage for control pin gnd 200 mv i ih input high current ? 150 150 a i il input low current ? 150 150 a termination resistors r tin internal input termination resistor 45 50 55 r tout internal output termination resistor 45 50 55 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input and output parameters vary 1:1 with v cc . 6. cml outputs loaded with 50 ? to v cc for proper operation. 7. vth, v ih , v il,, and v ise parameters must be complied with simultaneously. 8. vth is applied to the complementary input when operating in single ? ended mode. 9. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously. 10. v cmr min varies 1:1 with gnd, v cmr max varies 1:1 with v cc . the v cmr range is referenced to the most positive side of the differential input signal.
nb7v33m http://onsemi.com 5 table 6. ac characteristics v cc = 1.71 v to 2.625 v; gnd = 0 v; t a = ? 40 c to 85 c (note 11) symbol characteristic min typ max unit f max maximum input clock frequency 10 11 ghz v outpp output voltage amplitude (@ v inppmin ) f in 10 ghz (note 12) (figure 3) 260 400 mv t plh , t phl propagation delay to differential outputs, @ 1 ghz, measured at differential crosspoint clk/clk to q, q r to q, q 150 500 200 600 350 700 ps t plh tc propagation delay temperature coefficient 50 f s/ c t skew duty cycle skew (note 13) device ? device skew (tpdmax ? tpdmin) 20 50 ps t rr reset recovery (see figure 16) 550 135 ps t pw minimum pulse width r 500 200 ps t dc output clock duty cycle (reference duty cycle = 50%) f in 10 ghz 45 50 55 % n phase noise, f c = 1 ghz 10 khz 100 khz 1 mhz 10 mhz 20 mhz 40 mhz ? 144 ? 147 ? 152 ? 152 ? 152 ? 153 dbc t n integrated phase jitter (figure x) f c = 1 ghz, 12 khz ? 20 mhz offset 35 fs t jitter rj ? output random jitter (note 14) f in 10.0 ghz 0.2 0.8 ps rms v inpp input voltage swing (differential configuration) (figure 11) (note 15) 200 1200 mv t r , t f output rise/fall times @ 1 ghz (20% ? 80%), q, q 20 35 60 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. measured using a 1 ghz, v inpp min, 50% duty ? cycle clock source. all output loading with external 50 to v cc . input edge rates 40 ps (20% ? 80%). 12. output voltage swing is a single ? ended measurement operating in differential mode. 13. duty cycle skew is defined only for differential operation when the delays are measured from cross ? point of the inputs to the cross ? point of the outputs. duty cycle skew is measured between differential outputs using the deviations of the sum of tpw ? and tpw+ @ 1 ghz. skew is measured between outputs under identical transitions and conditions. 14. additive rms jitter with 50% duty cycle clock signal. 15. input voltage swing is a single ? ended measurement operating in differential mode. f in , clock input frequency (ghz) v outpp , output voltage amplitude (mv) 500 450 400 350 300 250 200 0246810 figure 3. output voltage amplitude (v outpp ) vs. input frequency (f in ) at ambient temperature (typical)
nb7v33m http://onsemi.com 6 figure 4. input structure 50 50 vtclk vtclk v cc clk clk i clk v th clk v th figure 5. differential input driven single ? ended v ih v il v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v thmax v thmin gnd v th figure 6. v th diagram clk clk figure 7. differential inputs driven differentially v ild(max) v ihd(max) v ihd v ild v ihd(min) v ild(min) v cmr gnd v id = v ihd ? v ild v cc clk clk q q t plh t phl v outpp = v oh (q) ? v ol (q) v inpp = v ih (clk) ? v il (clk) figure 8. differential inputs driven differentially figure 9. v cmr diagram figure 10. ac reference measurement v ihd v ild v id = |v ihd(d) ? v ild(d) | clk clk
nb7v33m http://onsemi.com 7 lvpecl driver v cc v ee z o = 50 v th = v cc ? 2 v z o = 50 nb7v33m clk 50 50 clk gnd figure 11. lvpecl interface lvds driver v cc gnd z o = 50 z o = 50 nb7v33m 50 50 gnd figure 12. lvds interface v cc v cc figure 13. standard 50 load cml interface figure 14. capacitor ? coupled differential interface (v tclk /v tclk connected to v refac ; v refac bypassed to ground with 0.1 f capacitor) figure 15. capacitor ? coupled single ? ended interface (v tclk /v tclk connected to v refac ; v refac bypassed to ground with 0.1 f capacitor) v tclk v tclk clk clk v tclk v tclk cml driver v cc gnd z o = 50 v t = v t = v cc z o = 50 nb7v33m 50 50 gnd v cc clk clk v tclk v tclk v cc differential driver v cc gnd z o = 50 v th = v refac z o = 50 nb7v33m 50 50 gnd v cc clk clk v tclk v tclk v th v tclk v tclk v th single ? ended driver v cc gnd z o = 50 v th = v refac nb7v33m 50 50 gnd v cc clk clk v th
nb7v33m http://onsemi.com 8 figure 16. ac reference measurement (timing diagram) t phl t plh t rr(min) 50% 50% 50% 50% 50% q clk r v outpp = v oh (q) ? v ol (q) v inpp = v ih (clk) ? v il (clk) figure 17. typical cml output structure and termination v cc 50 50 16 ma 50 50 v cc (receiver) gnd
nb7v33m http://onsemi.com 9 driver device receiver device qd figure 18. typical termination for cml output driver and device evaluation q d v cc 50 50 z = 50 z = 50 dut device ordering information1 device package shipping ? NB7V33MMNG qfn ? 16 (pb ? free) 123 units / rail nb7v33mmnhtbg qfn ? 16 (pb ? free) 100 / tape & reel nb7v33mmntxg qfn ? 16 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb7v33m http://onsemi.com 10 package dimensions 16 pin qfn case 485g ? 01 issue d 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag ??? ??? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k l 0.30 0.50 exposed pad 0.18 typ l1 detail a l alternate terminal constructions ?? 0.00 0.15 mm inches scale 10:1 0.50 0.02 0.575 0.022 1.50 0.059 3.25 0.128 0.30 0.012 3.25 0.128 0.30 0.012 exposed pad *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nb7v33m/d the products described herein (nb7v33m), may be covered by u.s. patents including 6,362,644 . there may be other patents pending. gigacomm is a trademark of semiconductor component industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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